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Sub-5nm All-Around Gate FinFET for Ultimate Scaling

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19 Author(s)
Hyunjin Lee ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon ; Lee-eun Yu ; Seong-Wan Ryu ; Jin-Woo Han
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Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO2 shows an IDsat of 497muA/mum at VG=V D=1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And a channel orientation effect, based on a current-flow direction, is shown

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VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

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