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Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

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13 Author(s)
J. Kavalieros ; Intel Corp., Hillsboro, OR ; B. Doyle ; S. Datta ; G. Dewey
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We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with IDSAT=1.4 mA/mum and 1.1 mA/mum respectively (IOFF=100nA/mum, VCC =1.1V and LG=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade ION-IOFF and DeltaS

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2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.

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