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A 4-Bit Double SONOS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation

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11 Author(s)
Oh, Chang Woo ; Device Res. Team, Samsung Electron. Co., Yongin ; Sung Hwan Kim ; Na Young Kim ; Yong Lack Choi
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We proposed a 4-bit double SONOS memory with two ONO layers, 4 storage nodes, for ultimate multi-bit operation and firstly demonstrate 4-bit operation using the physically separated 4 storage nodes. By using CHEI/HHI program/erase, each node was easily programmed and erased without any detrimental interference among the nodes. In the gate length of 120nm, the read/write margins of ~0.8V for front side (FS) and ~1.1V for back side (BS) at VDS=1.2V was obtained. The VTH shifts of ~1.5V for both program/erase (P/E) were observed with the P/E conditions, VD/VFG=3/5V, 3/-4V for FS and VD/VBG=3.2/7V, 3.2/-5V for BS, respectively, with the duration of 1 ms. The VTH windows of ~0.9V for FS and ~1.1V for BS were achieved even after 104 P/E cycles

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VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

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