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Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure

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12 Author(s)
Chang-Hyun Lee ; Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin ; Jungdal Choi ; Changseok Kang ; Yoocheol Shin
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For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO2/SiN/Al2O3/TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed. The evolved TANOS cells show four-level cell distribution which is free from program disturbance and a charge loss of less than 0.4 V at high temperature bake test

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VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

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