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Heat Generation and Transport in Nanometer-Scale Transistors

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3 Author(s)
E. Pop ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; S. Sinha ; K. E. Goodson

As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin body, FinFET, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomena including ballistic electron transport, which reshapes the heat generation region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. This paper surveys trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems

Published in:

Proceedings of the IEEE  (Volume:94 ,  Issue: 8 )