By Topic

A 1-V, 5.5-GHz, CMOS LNA With Multiple Magnetic Feedback

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
G. Vitzilaios ; Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ. ; Y. Papananos ; G. Theodoratos ; A. Vasilopoulos

A CMOS low-noise amplifier that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance is presented. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without noise figure (NF) degradation. Simulation results indicate voltage conversion gain of 17 dB, NF of 1.6 dB, and best-case third-order input intercept point of 13 dBm. The design is being implemented in a 0.13-mum CMOS technology

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:53 ,  Issue: 9 )