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High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems

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3 Author(s)
C. -H. Lin ; Graduate Inst. of Electron. Eng., Nat. Taiwan Univ. ; A. -Y. Wu ; F. -M. Li

This brief addresses the design of a decision feedback equalizer (DFE) for gigabit throughput rate. It is well known that the feedback loop in a DFE limits an upper bound of the achievable speed. For a L-tap feedbackward filter (FBF) and M-pulse amplitude modulation, Parhi (1991) and Kasturia and Winters (1991) reformulated the FBF as a (M)L-to-1 multiplexer. Due to the reformulation, the overhead of extra adders and extra multiplexers are as large as (M)L. The required hardware overhead should be more severe when the DFE is implemented in parallel. In this brief, we propose two new approaches to implement the DFE when gigabit throughput rate is desired. The first approach is partial pre-computation scheme, which can trade-off between hardware complexity and computational speed. The second approach is two-stage pre-computation scheme, which can be applied to higher speed applications. In the later case, we can reduce the hardware overhead to about 2(M)(-L/2) times of [1], [2], and the iteration bound is (log2W+2)/(L/2+1)+(log2M) multiplexer-delays, where W is the wordlength of weight coefficient of a FBF. We demonstrate the proposed architectures by apply it to the 10 Gbase-LX4 optical communication systems

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IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:53 ,  Issue: 9 )