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Design of CMOS Transistors to Maximize Circuit FOM Using a Coupled Process and Mixed-Mode Simulation Methodology

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3 Author(s)
Venugopal, R. ; Silicon Technol. Dev., Texas Instruments, Dallas, TX ; Chakravarthi, S. ; Chidambaram, P.R.

Calibrated process and device CMOS modules were integrated into a mixed-mode simulation setup to study the circuit figure of merit (FOM). Switching delay from typical two-input NAND, two-input NOR, and inverter circuits built and simulated in the device simulator Dessis, including both intra and intercell capacitances and resistances show strong dependence on the drain-induced barrier lowering and associated short-channel electrostatics. The analysis presented in this letter identifies, for a given set of leakage and process constraints, an optimal gate length (Lg) that maximizes circuit FOM. The analysis also highlights, for the first time, that the optimal Lg for maximizing circuit FOM is much longer than that required for maximizing the device performance. The optimal Lg for maximum circuit FOM is determined by a complex tradeoff between reduced capacitance, increased short-channel effect, and reduced mobility

Published in:

Electron Device Letters, IEEE  (Volume:27 ,  Issue: 10 )