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High-Linearity Performance of 0.13- \mu\hbox {m} CMOS Devices Using Field-Plate Technology

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3 Author(s)
Chien-Cheng Wei ; Dept. of Electron. Eng., Chang Gung Univ., Taoyuan ; Chiu, Hsien-Chin ; Wu-Shiung Feng

This letter presents high-linearity 0.13-mum CMOS devices based on field-plate technology. The field-plate technology reduces the electric field between the gate and drain terminals, subsequently forming a field-plate-induced depletion region and reducing the leakage current to significantly improve linearity and power of the CMOS devices. The third-order intermodulation product of 0.13-mum NMOS devices with and without field-plate technology are -41.8 and -32.4 dBm, respectively, for input power of -10 dBm. Experimental results indicate that the field-plate architecture exhibits high linearity and power for CMOS RFIC applications

Published in:

Electron Device Letters, IEEE  (Volume:27 ,  Issue: 10 )

Date of Publication:

Oct. 2006

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