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A 15-gb/s 2:1 multiplexer in 0.18-μm CMOS

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2 Author(s)
Jun-Chau Chien ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Liang-Hung Lu

By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18-mum CMOS process. With a power consumption of 110mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225mV and a root-mean-square jitter of 2.7ps

Published in:

IEEE Microwave and Wireless Components Letters  (Volume:16 ,  Issue: 10 )