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Analog AGC Circuitry for a CMOS WLAN Receiver

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3 Author(s)
O. Jeon ; Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL ; R. M. Fox ; B. A. Myers

The IEEE 802.11a standard uses orthogonal frequency division multiplexing (OFDM) to allow high data rates in multipath WLAN environments. The high peak-to-average power ratio (PAPR) of OFDM signals, along with stringent settling-time constraints, make conventional closed-loop automatic gain control (AGC) schemes impractical for WLAN receivers. In a direct conversion receiver, AGC and channel-select filtering are performed by analog baseband circuitry. A baseband signal processor using a new open-loop analog gain-control algorithm for OFDM is described. The new AGC algorithm uses switched coarse gain-setting steps followed by an analog open-loop fine gain-setting step to set the final gain of variable gain amplifiers (VGAs). The AGC was implemented in a 0.18-mum CMOS process using newly designed circuits including linear VGAs, RMS detectors, and current-mode computation circuitry. Simulation and measurement results verify that the new AGC circuit converges with gain error less than 1dB to the desired level within 5.6 mus

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 10 )