By Topic

Yield optimization using a GaAs process simulator coupled to a physical device model

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Stoneking, D.E. ; North Carolina State Univ., Raleigh, NC, USA ; Bilbro, G.L. ; Trew, R.J. ; Gilmore, P.
more authors

The enhancement of TEFLON, a physics-based large-signal GaAs MESFET model and circuit simulator that predicts and optimizes the yield of GaAs MESFET designs before fabrication, is discussed. Device acceptance criteria include both small- and large-signal RF operating characteristics such as small-signal gain, maximum power added efficiency, and output power at 1 dB gain compression. SUPREM 3.5, a process simulator, has been incorporated into TEFLON so that the MESFET channel donor distribution can be described directly from processing specifications for material deposition, ion implantation, and implant annealing. Monte Carlo techniques are used to estimate yield when disturbances in the MESFET parameters are modeled as multivariate Gaussian distributions. Finally, the yield estimator has been integrated with an optimizer so that a design can be centered for maximum yield in the presence of process disturbances

Published in:

High Speed Semiconductor Devices and Circuits, 1991., Proceedings IEEE/Cornell Conference on Advanced Concepts in

Date of Conference:

5-7 Aug 1991