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A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures

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3 Author(s)
A. Itradat ; Concordia University, Canada ; M. O. Ahmad ; A. Shatnawi

This paper presents a novel technique to obtain time schedules for cyclic DFGs representing DSP algorithms mapped onto multiprocessor systems with non-negligible inter-processor communication delays. In this paper, the question of optimizing the input/output delay in the presence of inter-processor communication overhead is addressed. The proposed technique operating on the cyclic DFG of a DSP algorithm is designed to evaluate the relative firing times of the nodes by using Floyd-Warshall's longest path algorithm so that the inter-processor communication overhead is taken into consideration to provide an optimal schedule

Published in:

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)

Date of Conference:

13-17 Sept. 2006