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Fast Matrix Multiplication in Dynamic SMP Clusters with Communication on the Fly in Systems on Chip Technology

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2 Author(s)
Tudruj, M. ; Inst. of Comput. Sci., Polish Acad. of Sci., Warsaw ; Masko, L.

This paper concerns numerical computations in a new shared memory system architecture oriented towards systems on chip technology. Dynamically reconfigurable processor clusters which adjust at program run-time to computation and communication requirements of programs and a new data exchange method between processors - called "communication on the fly" are main assumed architectural features. They provide a synergy of processor switching between clusters with data reads on the fly by many processors in the cluster while being written by the switched processor into memory. The paper presents results of simulated execution of matrix multiplication parallel program graphs. Considered graphs are based on two data decomposition methods: recursive division of matrices into squares and division into stripes. Elementary serial multiplications of square submatrices in parallel algorithms are done using Strassen method. The experiments show high efficiency of the proposed matrix multiplication method

Published in:

Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on

Date of Conference:

13-17 Sept. 2006