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A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments

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1 Author(s)
B. Fechner ; FernUniversität in Hagen, Germany

Modern microprocessors get more and more susceptible to transient faults, e.g. caused by high-energetic particles due to high integration, clock frequencies, temperature and decreasing voltage supplies. A newer method to speed up contemporary processors at small space increase is simultaneous multithreading (SMT). With the introduction of SMT, instruction fetch- and issue policies gained importance. SMT processors are able to simultaneously fetch and issue instructions from multiple instruction streams. In this work, we focus on how dynamic bus arbitration and scheduling of hardware threads within the processors front-end can help to dynamically adjust fault coverage and performance. The novelties which help to reach this goal are: a multi-bus-scheduling scheme which can be used to tolerate permanent bus faults and single event disturbances (SEDs). The second novelty can be used in conjunction with the first: a dynamic fetch scheduling algorithm for a simultaneous multithreaded processor, leading to the introduction of dynamic multithreading. Dynamically multithreaded processors are able to switch between different SMT fetch policies, thus enabling a graceful degradation of the processors front-end

Published in:

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)

Date of Conference:

13-17 Sept. 2006