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A 256kb Sub-threshold SRAM in 65nm CMOS

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2 Author(s)
Calhoun, B.H. ; Massachusetts Inst. of Technol., Cambridge, MA ; Chandrakasan, A.

A 256kb sub-threshold SRAM operates below 400mV from 0 to 85degC and is implemented in 65nm CMOS technology. For the same 6sigma static-noise margin, the sub-threshold SRAM at 0.4V achieves 2.25-times lower leakage power and 2.25-times lower active energy than its 6T counterpart at 0.6V. The SRAM uses a 10T bitcell to enable sub-threshold functionality

Published in:

Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International

Date of Conference:

6-9 Feb. 2006