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A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process

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3 Author(s)

A high-speed 4b flash ADC in 90nm digital CMOS is presented that uses a dynamic offset-compensation scheme in its comparators. It achieves a sampling rate of 1.25GS/s with 3.7 ENOB (23.8dB SNDR) from dc to Nyquist while consuming 2.5mW. It has an energy per conversion step of 0.16pJ

Published in:

Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International

Date of Conference:

6-9 Feb. 2006