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A Clock Duty-Cycle Correction and Adjustment Circuit

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4 Author(s)
Humble, J.S. ; Mayo Clinic, Rochester, MN ; Zabinski, P.J. ; Gilbert, B.K. ; Daniel, E.S.

A clock duty-cycle correction circuit that accepts input duty cycles ranging from 30% to 70% and maintains a user-selectable output duty cycle over a frequency range of 500MHz to 6GHz is demonstrated. The output duty cycle is selectable from 41.25% to 58.75% in 1.25% increments. The circuitry is integrated into a clock-distribution chip which provides 10 identical outputs

Published in:

Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International

Date of Conference:

6-9 Feb. 2006