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A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS

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5 Author(s)

A 12b 40MS/s 2-step subranging ADC is realized in a 90nm digital CMOS process. It uses a 7b coarse quantizer with a high-gain offset-canceling positive-feedback amplifier. ENOB is 10.2b at a 0.7V supply and 11.0b at a 1.0V supply. The ADC consumes 30mW at 40MS/s

Published in:

Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International

Date of Conference:

6-9 Feb. 2006