Analysis and correction of VLSI delay measurement errors due to transmission-line effects

In the testing of VLSI chips that have more than 128 pins, it is necessary to measure the signals from the devices under test (DUT) at the far end of transmission lines 50 cm or more away from the contact pads. The measurement suffers form waveform distortions and errors that are caused by the intrinsic delay of the transmission lines and the loading conditions at both ends of the transmission lines. This problem is analyzed using mathematical models, and the results are applied to correct the measurement errors with computer aid. A technique is presented to evaluate the true output delay time of the DUT under specified loading conditions, using the measured data from an imperfect measurement setup. Computer simulation results indicate that this technique is accurate and can be applied to practical VLSI measurements