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A 0.18/spl mu/m CMOS 10Gb/s 1:4 DEMUX using replica-bias circuits for optical receiver

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3 Author(s)
Hong, Ju-Pyo ; Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon ; Kyung-Soo Ha ; Lee-Sup Kim

This paper presents a 0.18mum CMOS 10Gb/s 1:4 demultiplexer using window blocking for stable level swing and replica bias circuit for specific swing level maintenance. A modified current mode logic (CML) is proposed for the high-speed operation of demultiplexer. It prevents holding incorrect data during data transition. Replica bias circuit consists of feedback circuit using simple comparator. The 1:4 demultiplexer is a binary tree type. It consumes 12.24mW in 10Gb/s data rates with 1.8V supply voltage

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006