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High-pass /spl Delta//spl Sigma/ modulator: from system analysis to circuit design

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3 Author(s)
V. T. Nguyen ; Departement Commun. et electronique, Telecom Paris, France ; P. Loumeau ; J. -F. Naviner

This paper describes a successful switched-capacitor implementation in CMOS process of a high-pass DeltaSigma modulator that is completely immune to low frequency noise. This is a second-order modulator which achieves a 59dB dynamic range with a 32 times oversampling ratio at 10 MHz sampling frequency. The relationship between the performance and the stability of the modulator and its circuit parameters was determined through a set of behavioral models. Efficient multilevel abstraction models were developed. They reduce simulation time and allow us to determine a possible range of circuit specifications with reasonable design margins with a view to circuit implementation. The modulator was implemented in a 0.35mum 3.3V CMOS process. Measurement shows that this modulator is completely immune to low frequency noise

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006