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A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique

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2 Author(s)
Jin-Fu Lin ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan ; Soon-Jyh Chang

In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the high-linearity requirement of the op-amp, a new type of SHA circuit is presented

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006