By Topic

A 10-bit pipeline A/D converter without timing signals

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Picolli, L. ; Dept. of Electron., Pavia Univ. ; Maloberti, F. ; Rossini, A. ; Borghetti, F.
more authors

This paper presents a novel 10-bit pipeline A/D converter for low noise, self-triggered applications. The proposed A/D converter does not require any timing signal (clock) in order to carry out the conversion, assuming that a sampled signal is provided at the input. The circuit basically operates as "combinatorial logic", propagating the partial conversions and the residues through the various stages asynchronously. The presented ADC has been designed in a standard 0.35 mum CMOS technology and the conversion period is lower than 500 ns (i.e. 2 MHz data rate). The power consumption is 39 mW from a 3.3 V power supply. The total chip area without pads is 2.24 mm2

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006