By Topic

A 19.5mW 1.5V 10-bit pipeline ADC for DVB-H systems in 0.35 /spl mu/m CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Adeniran, O.A. ; Dept. of Electron. & Electr. Eng., Univ. Coll. London ; Demosthenous, A.

This paper describes a 10-bit analog-to-digital converter (ADC) for digital video broadcasting-handheld (DVB-H) systems. The ADC is based on a 2.5-2.5-2.5-4 bits-per-stage pipeline architecture and occupies an area of 1.3 mm2 in a 0.35 mum CMOS process. At the target sampling rate of 20.48 MS/s, measured results show that the converter consumes 19.5 mW from a 1.5 V power supply and achieves 56 dB SNR and 60 dB SFDR. Effective resolution bandwidth is 100 MHz and energy consumption per conversion is 0.19 pJ

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006