Digital background calibration of pipeline ADC with open-loop gain stage

In this work, a digital background calibration method for pipelined ADC is proposed which can compensate for the nonlinearity in amplifier gain. The proposed scheme is based on input statistical distribution property which is assumed to be known. The error correction is completely performed in digital domain. In analog domain it is only necessary to add two comparators for generating calibration threshold. Results show an improvement of 16 dB in SNDR for a nonlinear gain stage designed in a 1.5 V supply and 0.35 mum CMOS technology