By Topic

Digital background calibration of pipeline ADC with open-loop gain stage

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tavassoli, B. ; Dept. of ECE, Tehran Univ. ; Shoaei, O.

In this work, a digital background calibration method for pipelined ADC is proposed which can compensate for the nonlinearity in amplifier gain. The proposed scheme is based on input statistical distribution property which is assumed to be known. The error correction is completely performed in digital domain. In analog domain it is only necessary to add two comparators for generating calibration threshold. Results show an improvement of 16 dB in SNDR for a nonlinear gain stage designed in a 1.5 V supply and 0.35 mum CMOS technology

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006