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A 1.7mW all digital phase-locked loop with new gain generator and low power DCO

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2 Author(s)
Tzu-Chiang Chao ; Dept. of Electron. Eng., National Chiao-Tung Univ., HsinChu, Taiwan ; Wei Hwang

In this paper, a new architecture and algorithm for all digital phase-locked loop (ADPLL) is proposed. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, we can combine the functions of the frequency comparator, phase detector and gain generator in one hard block. Also, a new digitally controlled oscillator (DCO) structure for low power, small area is presented and its frequency range is from 200 MHz to 750 MHz with a supply voltage 1.2v. The total power consumption of ADPLL is 1.7mW. This ADPLL has characteristics of fast frequency locking, small hard cost and lower power consumption. This ADPLL is designed and implemented by TSMC's 0.13mum CMOS technology

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006