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2-level FIFO architecture design for switch fabrics in network-on-chip

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2 Author(s)
Po-Tsang Huang ; Dept. of Electron. Eng., National Chiao-Tung Univ., Hsinchu ; Wei Hwang

The network-on-chip (NoC) architecture provides the integrated solution for system-on-chip (SoC) design. The buffer architecture and sizes, however, dominate the performance of NoC and influence on the design of arbiters in the switch fabrics. The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures without increasing the buffer sizes. The concept of the shared memory mechanism and multiple accesses for the buffers are developed. The FIFO architecture is implemented and simulated with TSMC 0.13mum network-on-chip by HSPICE and Verilog. The operation frequency of the 2-level FIFO reaches 400MHz

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006