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Parallel encoders for low-density parity-check convolutional codes

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2 Author(s)
Bates, S. ; Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta. ; Swamy, R.

Low-density parity-check convolutional codes combine the good bit error rate performance of low-density parity-check block codes with the ability to encode and decode arbitrary lengths of data. This makes them attractive in applications where the data unit to be encoded varies in length. In this paper we discuss the parallelization of encoders for low-density parity-check convolutional code. We then present results to show how this parallelism impacts on the area and throughput of VLSI implementations of these encoders. We show how this technique can be used to implement encoders with throughputs suitable for next-generation communication standards and other high-speed applications

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006