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A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm

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4 Author(s)
Chi-Hong Chan ; Dept. of Electron. Eng., Chinese Univ. of Hong Kong, China ; Cheong-Fat Chan ; Chiu-Sing Choy ; Kong-Pang Pun

This paper presents a current-mode analog-to-quaternary (A/Q) converter using a 0.35mum CMOS process. Redundant signed digit (RSD) technique is used to improve the resolution to 6 digits, which is equivalent to 12 binary bits. Simulations results show that the converter dissipates 382mW at 2.5V supply and 20MHz sampling rate. The converter achieves SNDR of 66.8dB, SFDR of 76.33dB and THD of -75.73dB. The effective number of bit is equal to 5.4 digits or 10.8 bits (binary)

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006