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A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution

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2 Author(s)
Ali, S. ; Dept. of Electr. & Comput. Eng., Rochester Univ., NY ; Margala, M.

A novel single chip 2.4-GHz phase-lock loop (PLL) with auto-calibration mechanism, which is adaptive to process variation, is presented. The proposed synthesizer with self-calibration block is connected to the on-chip jitter measurement circuit. The PLL adjusts the voltage controlled oscillator (VCO) input control voltage in response to the measured jitter by the jitter measurement block. The response of the VCO is adjusted inherently towards the desired center frequency by the self-calibration process to reduce the jitter of its 2.4-GHz output for ZigBee application. This method could also be used to implement built-in-self-test for PLL. The synthesizer, designed in TSMC 0.18-mum technology, has an edge jitter standard deviation of 0.86-ps having a 20% improvement over PLL with no self-calibration. The digitally controlled VCO has a wide tuning range of 0.6-GHz. The synthesizer has a programmable frequency divider that operates with a division range of 456-496

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006