By Topic

A 4-Kb low power 4-T SRAM design with negative word-line gate drive

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Chua-Chin Wang ; Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan ; Ching-Li Lee ; Wun-Ji Lin

The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line gate drive to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-Kb 4-T SRAM is measured to consume 0.12 mW in the standby mode, and a 3.8 ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006