A 4-Kb low power 4-T SRAM design with negative word-line gate drive

The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line gate drive to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-Kb 4-T SRAM is measured to consume 0.12 mW in the standby mode, and a 3.8 ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz.