By Topic

1-V ultra-low-power CMOS LC VCO for UHF quadrature signal generation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Zheng Wang ; ECE Dept., NC A&T State Univ., Greensboro, NC ; Savci, H.S. ; Dogan, N.S.

Design, implementation, and simulation of ultra-low-power LC-VCOs with quadrature signal generation are presented, as well as the analysis and the comparison of several different VCO topologies. The VCO topology having the best performance is then used further for quadrature signal generation. Based on a 0.18mum RF/mixed-signal CMOS process, the VCOs are simulated using 1V supply voltage. It is demonstrated that the N- & P- MOS cross-coupled pair VCO with balance resistors operating at 1.6GHz has a power consumption of 0.1mW with as low as -121 dBc/Hz of phase noise at 1-MHz offset. To generate the quadrature signals at 400MHz, N- & P- MOS pair VCOs at the frequency of 400MHz, 800MHz, 1.6GHz, divide-by-two, and divide-by-four circuits are implemented and compared. It turns out that the frequency dividers degrade the phase noise. Comparison of FOMs shows that VCO at 800MHz followed by a divide-by-two is the best choice for quadrature signal generation at 400 MHz, achieving 177muW for the VCO and 25muW for the divider. The phase noise is -127dBc/Hz at 1-MHz offset

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006