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NIUGAP: low latency network interface architecture with Gray code for networks-on-chip

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3 Author(s)
Daewook Kim ; Dept. of Electr. & Comput. Eng., Minnesota Univ., USA ; Manho Kim ; G. E. Sobelman

The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP cores. In this paper, we present a novel NIU architecture that utilizes a Gray code based packet reordering methodology to achieve low latency packet processing. The proposed architecture has been implemented with VHDL and synthesized using a 0.25 mum ASIC technology. Simulation results verify the functionality of the architecture and show that it can save a substantial amount of packet processing time compared to the conventional reordering scheme

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006