Efficient architecture for Reed Solomon block turbo code

Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital communications and storage. Recently, block turbo codes using Reed-Solomon component codes have been introduced. This was motivated by the highest code rate property of Reed-Solomon codes and their efficiency for burst error correction. In fact, the main advantage of Reed-Solomon block turbo codes is for high code rate applications. For these applications, the code length and consequently the decoder complexity are smaller than for usual Bose-Chaudhuri-Hocquenghem block turbo codes. This paper presents a block turbo decoder architecture using Reed-Solomon component codes. Our elementary soft input soft output decoder is dedicated to Reed-Solomon codes (31, 29, 3) with single error correction power. To the authors' knowledge, this is the first published architecture implementing this type of decoder. Experimentation has been done on a Stratix-based NIOS development board