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A stream register file unit for reconfigurable processors

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7 Author(s)
F. Campi ; STMicroelectronics, Agrate Brianza, Italy ; P. Zoffoli ; C. Mucci ; M. Bocchi
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This paper presents a local buffer memory in the form of a stream register file (SRF) that was developed in order to connect, in a compiler-friendly pattern, large-bandwidth run-time configurable logic units in processor-based SOCs. The proposed SRF offers to the host SOC system performance speedups in the range of 4times, with area/power overhead in the order of 6%. The described hardware and algorithm mapping strategy was implemented on silicon in a SOC based on the PiCoGA reconfigurable architecture. The SOC provides an average 450 MOPS (mega operations per Second) in STM CMOS090 technology running at 100MHZ

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006