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Mapping DSP applications on processor/coarse-grain reconfigurable array architectures

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3 Author(s)
Galanis, M.D. ; Dept. of Electr. & Comput. Eng., Patras Univ. ; Dimitroulakos, G. ; Goutis, C.E.

Results from mapping five real-world DSP applications on a system-on-chip that incorporates coarse-grain reconfigurable hardware with an instruction-set processor is presented. The reconfigurable logic is realized by a 2-dimensional array of processing elements. A mapping method for improving application's performance by accelerating critical software parts, called kernels, on the coarse-grain reconfigurable array is proposed. For mapping the detected kernels on the reconfigurable logic a priority-based mapping algorithm has been developed. Important overall application speedups, due to the kernels' acceleration, have been reported for the five applications. These overall performance improvements range from 1.27 to 3.07, with an average value of 2.16, relative to an all-software execution

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006