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Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology

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2 Author(s)
Chung, B. ; Sch. of Eng. Sci., SFU, Burnaby, BC ; Kuo, J.B.

This paper reports a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique, for designing high-speed low-power SOC applications using 90nm MTCMOS technology. Based on this optimization technique, using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less power consumption as compared to the all low-threshold one

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006

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