A CMOS circuit for embedded GHz measurement of digital signal rise time degradation

An embedded diagnosis circuit for quantifying the degradation in digital signals rise/fall time is presented. The proposed measurement technique differs from previous approaches in many ways. Firstly, it avoids the use of undersampling which can become problematic at high speeds; instead, it relies on a real-time asynchronous sampling approach which eliminates the distortion jeopardy imposed by the front-end sampling network, sampling clock jitter, and delay line jitter for GHz range applications. Secondly, the information is processed in the time domain which makes use of the recent developments in time-domain amplification (Oulmane and Roberts, 2004). Thirdly, a dynamic current generation technique is used to achieve great reduction in static power dissipation and allows the front-end level-crossing detector to work at such high speeds. The circuit was implemented in a standard 0.18-mum CMOS process. Simulation results show the feasibility of the proposed approach. Preliminary experimental results are also presented. The proposed circuit can be equally used to perform on-chip analog slew rate measurement