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A low-power geometric mapping co-processor for high-speed graphics application

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2 Author(s)
Leeke, S. ; Bristol Univ. ; Maharatna, K.

In this article we present a design of a low-power geometric mapping co-processor that can be used for high-performance graphics system. The processor can carry out any single or a combination of transformations belonging to affine transformation family ranging from 1D to 3D. It allows interactive operations which can be defined either by a user (allowing it to be a stand-alone geometric transformation processor) or by a host processor (allowing it to be a co-processor to accelerate certain graphics operations). It occupies a silicon area of 6 mm2 and consumes 40 mW power when synthesized with 0.25mum technology

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006