Cart (Loading....) | Create Account
Close category search window

1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-/spl mu/m CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Pyung-Su Han ; Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul ; Woo-Young Choi

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0deg and 180deg according to the current clock phase. A prototype chip was designed with 0.18-mum CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.