1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-/spl mu/m CMOS

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0/spl deg/ and 180/spl deg/ according to the current clock phase. A prototype chip was designed with 0.18-/spl mu/m CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement.