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1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-/spl mu/m CMOS

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2 Author(s)
Pyung-Su Han ; Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul ; Woo-Young Choi

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0deg and 180deg according to the current clock phase. A prototype chip was designed with 0.18-mum CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006

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