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Efficient memory architecture for JPEG2000 entropy codec

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6 Author(s)
Sugano, H. ; Dept. of Commun. & Comput. Eng., Kyoto Univ. ; Tsutsui, H. ; Masuzaki, T. ; Onoye, T.
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An encoding/decoding process of JPEG2000 requires much more computation power than that of conventional JPEG mainly due to the complexity of entropy encoding/decoding. Thus usually multiple entropy codec hardware modules are implemented in parallel to process entropy encoding/decoding. This module, however, requests many small-size memories to store intermediate data, and when multiple modules are implemented on a chip, employment of the large number of SRAMs increases difficulty of whole chip layout. In this paper, an efficient memory architecture of the entropy encoding/decoding module is proposed, in which three approaches are attempted by utilizing one-bank SRAMs and internal registers. As a result, the efficient memory organization for a target process technology can be explored

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006