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A 2-GHz CMOS variable gain amplifier optimized for low noise

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2 Author(s)
C. T. Charles ; Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA ; D. J. Allstot

An analysis of the noise performances of the current steering and simple cascode variable gain amplifier topologies is presented. Simulation results are used to determine the dominant noise sources at reduced gain levels, and analytical techniques are used to obtain a sizing strategy for minimizing the overall noise figure. The optimum configuration is shown to be a current steering topology with unequal sizing for the current steering transistors. Using simulations for the final sizing optimization, a current steering variable gain amplifier has been designed in 0.18 mum CMOS technology. The amplifier consumes 8 mW of power, has a maximum S21 of 20.6 dB, a noise figure of 1.47 dB at the maximum gain, and a noise figure of 8.8 dB when the gain is reduced by 20 dB

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006