By Topic

A bidirectional linear semi-systolic architecture for DCT-domain image resizing processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Das, A.K. ; Sch. of Inf. Technol., Indian Inst. of Technol., Kharagpur ; Ghosh, S.K.

In recent times, there is an increasing interest in compressed-domain image analysis and its VLSI implementation due to extensive use multimedia communication, specially in mobile devices. This paper deals with the semi systolic architecture of DCT-based (discrete cosine transform) image resizing processor as a compressed domain image processing element. Further, we propose an efficient method for VLSI implementation for DCT-domain image resizing transformation with bidirectional linear semi-systolic array. This method is developed from the investigation of the DCT-domain image resizing operation through a parallel processing of the matrix operations. The use of systolic arrays as a processing block of the matrix operations reduces the number of computation and also amenable for VLSI implementation

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006