By Topic

Low-voltage floating-gate CMOS buffer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ozalevli, E. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA ; Qureshi, M.S. ; Hasler, P.E.

This paper describes an implementation of a low-voltage CMOS buffer employing a negative feedback to improve its performance. Floating-gate transistors are incorporated to obtain low-threshold transistors and to increase the input/output voltage swing of the circuit operating at 1.2V. The designed circuit is fabricated in 0.5mum CMOS process, and occupies 0.0214mm2. It achieves total harmonic distortion (THD) of 48dB for 10kHz 0.6Vpp sinusoidal input signal

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006