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FPGA implementation of FIR filter using M-bit parallel distributed arithmetic

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3 Author(s)
Shiann-Shiun Jeng ; Dept. of Electr. Eng., National Dong Hwa Univ., Hualien ; Hsing-Chen Lin ; Shu-Ming Chang

An efficient architecture for a FPGA symmetry FIR filter is proposed that employs M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed RAM. This eliminates the large amount of logic needed to compute multiplication results. The proposed architecture consumes less area and offers higher speed operation because the multiplier is omitted. Altera APEX20KE is used as a target device. Thus, the proposed architecture has high processing speed and small area

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006

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