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Low power architectures using localised non-volatile memory and selective power shut-down

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2 Author(s)

A method and associated circuit and architectural implementations to reduce the power dissipation for the digital part of a system-on-a-chip (SOC) while maintaining the overall system performances (such as speed) unaffected are described. An alternative application is to provide fast recovery from a power shut-down event up to the level of instruction (or clock cycle) execution

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006