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Low power binary addition using carry increment adders

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2 Author(s)
Grad, J. ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL ; Stine, J.E.

Sparse prefix tree adders like carry-select adders and carry-increment adders are commonly used in the implementation of high-speed parallel adders. This paper presents a novel Ling carry-increment adder, which further reduces the area and power consumption as compared to a conventional carry-increment adder. The proposed algorithm utilizes Ling pseudo-carries in both the prefix tree and the output sum blocks. The algorithm is verified with the implementation of two 64-bit adders using the conventional carry-increment and the proposed Ling carry-increment algorithms. An 8-bit sum block using the proposed algorithm uses 7% fewer devices and consumes 16% less energy, while the complete adder uses 8% fewer transistors and consumes 7% less energy

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006