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Implementation of a high-speed low-power 32-bit adder in 70nm technology

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2 Author(s)
F. Kashfi ; Sch. of ECE, Tehran Univ., Iran ; S. Mehdi Fakhraie

In this article, the performance and power dissipation of two differential logic circuits in deep sub-micron technologies are obtained and compared together, and the superior topology is introduced. Low voltage swing (LVS) technique which improves circuit performance and lowers power consumption is described in detail. We conclude this article with the design, simulation and optimization of a high speed low-power 32-bit adder using the LVS technique in 70nm technology. This circuit can operate at 10GHz clock frequency with power dissipation as low as 2.58 mW/GHz

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006