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Multiplier reduction tree with logarithmic logic depth and regular connectivity

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6 Author(s)
Eriksson, H. ; Dept. of Comput. Sci. & Eng., Chalmers Univ. of Technol., Goteborg ; Larsson-Edefors, P. ; Sheeran, M. ; Sjalander, M.
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A novel partial-product reduction circuit for use in integer multiplication is presented. The high-performance multiplier (HPM) reduction tree has the ease of layout of a simple carry-save reduction array, but is in fact a high-speed low-power Dadda-style tree having a worst-case delay which depends on the logarithm (O(log TV)) of the word length N

Published in:

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Date of Conference:

21-24 May 2006